Title0.0068mm2自校准电路在锁相环中的应用
Other TitlesA 0.0068 mm2 Self-calibration Circuit for Phase Locked Loop
Authors郑佳鹏
李伟
杨翼
马俊程
程玉华
王阳元
Affiliation北京大学信息科学技术学院微电子学研究院,北京,100871
中芯国际,上海,201203
Keywords锁相环
自校准
振荡环
PLL
self-calibrations
ring oscillator
Issue Date2011
Publisher北京大学学报自然科学版
Citation北京大学学报(自然科学版).2011,47,(1),29-34.
Abstract提出了一种可供CMOS锁相环使用的自由调整的自校准技术.与传统的自校准技术相比,新的自校准方案不需要使用参考电压源,而且自校准过程内嵌在锁相环的锁定过程中,所以新的自校准方案减少了芯片的面积:与自校准有关电路的面积只有0.0068 mm<'2>.所设计的PLL采用0.13μm CMOS工艺,工作频率范围在25~700MHz之间.测试表明,当压控振荡器工作在700 MHz的时候,其8倍降频之后的87.5 MHz输出信号的相位噪音在1 MHz频率偏移处为-131 dBc/Hz.
A phase locked loop (PLL) using a free-running self-calibration technique is reported. The proposed self- calibration operation is performed during the process of the normal PLL lock period without requiring a voltage-reference block. The new scheme benefits reducing chip area. The area interrelated to calibration circuits is only 0.0068 mm<'2>. The PLL is designed and implemented using SMIC 0.13μm complementary metal oxide semiconductor (CMOS) process and the measured PLL lock-in frequency range is 25-700 MHz. The phase noise of the output clock at 87.5 MHz is-131 dBc/ Hz at 1 MHz offset, while the voltage-controlled-oscillator (VCO) is at 700 MHz.
URIhttp://hdl.handle.net/20.500.11897/23413
ISSN0479-8023
Appears in Collections:信息科学技术学院

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