Showing results 1 to 20 of 123
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| Issue Date | Title | Author(s) |
| Aug-2022 | A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications | Xiao, Kanglin; Cui, Xiaoxin; Qiao, Xin; Wang, Xin 'an; Wang, Yuan |
| 2024 | A 16.41 TOPS/W CNN Accelerator with Event-Based Layer Fusion for Real -Time Inference | Wang, Jiawei; Lun, Li; Dai, Zhenhui; Jiang, Yuanyuan; Cui, Xiaoxin |
| 2007 | A 2-level FSK demodulator for digital-IF receiver | Cui, Xiaoxin; Yu, Dunshan; Zhang, Xing |
| 25-Oct-2021 | 28 nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance | Zou, Qingyun; Cui, Xiaoxin; Dai, Zhenhui; Kuang, Yisong; Zhong, Yi; Zou, Chenglong; Cui, Xiaole |
| Jul-2024 | A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations | Xiao, Kanglin; Qiao, Xin; Cui, Xiaoxin; Song, Jiahao; Luo, Haoyang; Wang, Xin'an; Wang, Yuan |
| Jul-2021 | A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS | Kuang, Yisong; Cui, Xiaoxin; Zhong, Yi; Liu, Kefei; Zou, Chenglong; Dai, Zhenhui; Wang, Yuan; Yu, Dunshan; Huang, Ru |
| Jun-2022 | A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling | Qiao, Xin; Song, Jiahao; Tang, Xiyuan; Luo, Haoyang; Pan, Nanbing; Cui, Xiaoxin; Wang, Runsheng; Wang, Yuan |
| 2008 | An Acquisition Circuit in Global Positioning System Receivers | Cui, Xiaoxin; Peng, Chungan |
| 2010 | An adaptive edge enhancement algorithm and hardware implementation | Long, Jinkai; Cui, Xiaoxin; Yu, Dunshan |
| 2013 | AHardware implementation of des with combined countermeasure against DPA | Cui, Xiaoxin; Li, Rui; Wei, Wei; Gu, Juan; Cui, Xiaole |
| 17-Dec-2024 | An all integer-based spiking neural network with dynamic threshold adaptation | Zou, Chenglong; Cui, Xiaoxin; Feng, Shuo; Chen, Guang; Zhong, Yi; Dai, Zhenhui; Wang, Yuan |
| 2005 | Analysis on a Game Model for Software Test Process Based on ROI | Cui, Xiaole; Wang, Xinan; Zhang, Xing; Cui, Xiaoxin |
| 2021 | The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF | Cui, Xiaole; Chen, Yongliang; Ye, Wenqiang; Cui, Xiaoxin |
| 2006 | Application of high-level design of hardware with timed CSP | Cui, Xiaoxin; Yu, Dunshan; Cui, Xiaole; Sheng, Shimin |
| 2024 | The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice | Chen, Yongliang; Cui, Xiaole; Cui, Xiaoxin; Zhang, Xing |
| Dec-2023 | An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array | Zhang, Sunrui; Cui, Xiaole; Wei, Feng; Cui, Xiaoxin |
| 2019 | BINARY CONVOLUTIONAL NEURAL NETWORK FOR BRAIN COMPUTER INTERFACES | Zhao, Shiqi; Cui, Xiaoxin; Fan, Yuanning; Zou, Chenglong; Yu, Dunshan |
| 2013 | Carrier-aided smoothing for real-time Beidou positioning | Lei, Dengyun; Lu, Weijun; Cui, Xiaoxin; Yu, Dunshan |
| 2013 | A combined countermeasure against DPA and implementation on des | Li, Rui; Cui, Xiaoxin; Wei, Wei; Wu, Di; Liao, Kai; Liao, Nan; Ma, Kaisheng; Yu, Dunshan; Cui, Xiaole |
| 2018 | A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition | Li, Cheng; Wang, Yuan; Zhang, Jin; Cui, Xiaoxin; Huang, Ru |
