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| Issue Date | Title | Author(s) |
| 2018 | A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process | Wang, Yuan; Jiang, Mengying; Liu, Baoguang; Jia, Song; Zhang, Xing |
| 2012 | A 1.25/2.5/3.125Gbps CDR circuit with a phase interpolator for RapidIO application | Yang, Hailing; Wang, Yuan; Jia, Song; Zhang, Ganggang; Zhang, Xing |
| 2015 | A 10b, 0.7ps Resolution Coarse-Fine Time-to-Digital Converter in 65nm CMOS using a Time residue Amplifier | Chen, Jiyu; Jia, Song; Wang, Yuan |
| 2015 | A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier | Chen, Jiyu; Jia, Song; Wang, Yuan |
| Aug-2022 | A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications | Xiao, Kanglin; Cui, Xiaoxin; Qiao, Xin; Wang, Xin 'an; Wang, Yuan |
| 2009 | A 16-bit 312.5-kHz Bandwidth Fourth-order One-Bit Switched-Capacitor Sigma-Delta Modulator | Li, Hongyi; Wang, Yuan; Jia, Song; Zhang, Xing |
| 2024 | A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation | Qiao, Xin; Guo, Qingyu; Tang, Xiyuan; Song, Jiahao; Wei, Renjie; Li, Meng; Wang, Runsheng; Wang, Yuan |
| 2021 | A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing | Song, Jiahao; Wang, Yuan; Tang, Xiyuan; Wang, Runsheng; Huang, Ru |
| 2015 | 180.5Mbps-8Gbps DLL-Based Clock and Data Recovery Circuit with Low Jitter Performance | Liu, Yuequan; Wang, Yuan; Jia, Song; Zhang, Xing |
| 2024 | A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation | Shen, Zilong; Tang, Jiajun; Luo, Haoyang; Wu, Zhongyi; Wang, Zongnan; Zhang, Xing; Tang, Xiyuan; Wang, Yuan |
| Feb-2023 | A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro | Song, Jiahao; Tang, Xiyuan; Qiao, Xin; Wang, Yuan; Wang, Runsheng; Huang, Ru |
| 2022 | A 28-nm 198.9-TOPS/W Fault-Tolerant Stochastic Computing Neural Network Processor | Hu, Yixuan; Zhang, Yawen; Wang, Runsheng; Zhang, Zuodong; Song, Jiahao; Tang, Xiyuan; Qian, Weikang; Wang, Yanzhi; Wang, Yuan; Huang, Ru |
| 2024 | A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI | Diao, Haikang; Luo, Haoyang; Song, Jiahao; Xu, Bocheng; Wang, Runsheng; Wang, Yuan; Tang, Xiyuan |
| Jul-2024 | A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations | Xiao, Kanglin; Qiao, Xin; Cui, Xiaoxin; Song, Jiahao; Luo, Haoyang; Wang, Xin'an; Wang, Yuan |
| 2022 | A 3T eDRAM In-Memory Physically Unclonable Function With Spatial Majority Voting Stabilization | Song, Jiahao; Luo, Haoyang; Tang, Xiyuan; Xu, Kuan; Ji, Zhigang; Wang, Yuan; Wang, Runsheng; Huang, Ru |
| 2023 | A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM | Song, Jiahao; Tang, Xiyuan; Luo, Haoyang; Zhang, Haoyi; Qiao, Xin; Sun, Zixuan; Yang, Xiangxing; Wu, Zihan; Wang, Yuan; Wang, Runsheng; Huang, Ru |
| 2016 | A 4.8-6.8GHz low phase noise LC VCO in 0.13-mu m CMOS technology | Wang, Yuan; Gan, Shanliang; Jia, Song; Zhang, Xing |
| Jul-2021 | A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS | Kuang, Yisong; Cui, Xiaoxin; Zhong, Yi; Liu, Kefei; Zou, Chenglong; Dai, Zhenhui; Wang, Yuan; Yu, Dunshan; Huang, Ru |
| Jun-2022 | A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling | Qiao, Xin; Song, Jiahao; Tang, Xiyuan; Luo, Haoyang; Pan, Nanbing; Cui, Xiaoxin; Wang, Runsheng; Wang, Yuan |
| May-2024 | A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC | Xue, Chang; Qiao, Xin; Ren, Xu; Du, Gang; Wang, Yuan; He, Yandong |
