| Title | High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis |
| Authors | Li, Meng Zhang, Peng Zhu, Chuang Jia, Huizhu Xie, Xiaodong Cong, Jason Gao, Wen |
| Affiliation | Peking Univ, Natl Engn Lab Video Technol, Beijing 100871, Peoples R China. Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90024 USA. UCLA PKU Joint Res Inst Sci & Engn, Los Angeles, CA USA. |
| Keywords | interpolation VLSI implementation High Level Synthesis FPGA UHD video scaling |
| Issue Date | 2015 |
| Publisher | 2015 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE) |
| Citation | 2015 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE).Las Vegas, NV,2015/1/1. |
| Abstract | Image scaling is a fundamental algorithm used in a large range of digital image applications. In this paper, we propose an efficient VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved design productivity compared to the traditional RTL-based design flow. So we explored a large design space including several fine-grained and coarse-grained optimizations in the pipeline architecture design. Our architecture is verified in a working system based on Xilinx Kintex-7 FPGA. Experiments show that our design can process UHD (3840* 2160) videos at 30fps with moderate resource utilization. |
| URI | http://hdl.handle.net/20.500.11897/423605 |
| ISSN | 2158-3994 |
| DOI | 10.1109/ICCE.2015.7066333 |
| Indexed | EI CPCI-S(ISTP) |
| Appears in Collections: | 信息科学技术学院 |
