| Title | A Calibration-Free Fractional-N ADPLL Using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator |
| Authors | Jiang, Haoyun Zhang, Zherui Shen, Zhengkun Hao, Xiucheng Liu, Zexue Li, Heyi Tan, Yi Zhou, Qiang Liu, Junhua Liao, Huailin |
| Affiliation | Peking Univ, Inst Microelect, Key Lab Microelect Devices & Circuits MOE, Beijing 100871, Peoples R China |
| Keywords | Calibration-free ADPLL Phase interpolator Retiming clock DPI DTC |
| Issue Date | 2019 |
| Publisher | 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
| Abstract | This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration. The DPI utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity. Designed in a 40-nm CMOS technology, the proposed DPI achieves 9-bit resolution, 0.3ps integral nonlinearity (INL) and 0.083ps differential nonlinearity (DNL). The proposed ADPLL achieves -118 dBc/Hz in-band phase noise at 1MHz and -93.9dBc fractional spur with the 0.3ps nonlinearity of DPI. |
| URI | http://hdl.handle.net/20.500.11897/544410 |
| ISSN | 0271-4302 |
| Indexed | CPCI-S(ISTP) |
| Appears in Collections: | 信息科学技术学院 |
