TitleA 12-Bit 0.5-2.4-GHz 0.65 degrees-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter
AuthorsJiang, Haoyun
Shen, Zhengkun
Wang, Dong
Hao, Xiucheng
Liu, Zexue
Tan, Yi
Liu, Junhua
Liao, Huailin
AffiliationPeking Univ, Inst Microelect, Beijing 100871, Peoples R China
Issue DateJan-2021
PublisherIEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
AbstractA 12-bit 0.5-2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm(2) and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65 degrees and a peak differential nonlinearity (DNL) of 0.25 degrees.
URIhttp://hdl.handle.net/20.500.11897/602342
ISSN1531-1309
DOI10.1109/LMWC.2020.3035609
IndexedEI
SCI(E)
Appears in Collections:信息科学技术学院

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