TitleA 0.014mm<sup>2</sup>10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR
AffiliationTsinghua University, Beijing, China
Peking University, Beijing, China
KeywordsEnergy efficiency
Analog to digital conversion - Signal to noise ratio - CMOS integrated circuits
Issue Date2022
PublisherDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Abstract<div data-language="eng" data-ev-field="abstract">High-resolution (&gt; 100dB SNDR), kHz-BW ADCs are required by emerging Io top and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of integration are also required, especially to be compatible with the advanced CMOS processes that the loT processor prefers. The state-of-the-art solutions in this scenario, such as the zoom ADC [1], the DT or CT-DSM [2]-[3], and the SAR ADC [4] and its noise-shaping variants [5], have already achieved great energy efficiency with &gt;180dB FOMs. However, most of them are large in area, and rely heavily on the analog performance of old CMOS technologies with high supply voltages. In this work, we propose a new architecture that combines the counting ADC and CT-incremental-DSM (CT-IDSM) in a zoom ADC framework. The proposed architecture is not only power efficient, but also compact in area, highly digital, and friendly to process down-scaling. It operates at Nyquist sampling, supporting single-shot conversion and channel multiplexing. Besides this, it provides a high-impedance input with full-scale common-mode rejection, allowing direct driving by many signal sources. Fabricated in 28nm CMOS, the prototype zoom-incremental-counting (ZIC) ADC is measured to have 103dB SNDR at 20kSa/s, consuming 475 W from a 0.9V supply. The resulting 176dB FOMs is comparable to the state-of-the-art designs. It occupies only 0.014mm2, which is a magnitude or two smaller than most reported ADCs with &gt; 90dB SNR.<br/></div> &copy; 2022 IEEE.
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